
B-63983EN/02 4.LADDER LANGUAGE
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4.1.4 WRT Instruction
(1) Format
C
B
R220.1 G2.2
Y11.1
Y14.6
X4.2
W2
W1
WRT
instruction
Fig. 4.1.4
Bit number
ddress numbe
.
(Address)
WR
(2) The WRT instruction outputs the result of the logical operation,
namely the status of the ST0 bit (0 or 1), to the specified address.
(3) The instruction can also output a logical operation result to two
or more addresses simultaneously. In that case, use the WRT
instruction as shown in Fig. 4.1.4 and Table 4.1.4.
Table 4.1.4
Mnemonic format Status of operation result
Step
number
Instruction
Address
No.
Bit No. Remarks ST2 ST1 ST0
1 RD R220 .1 A A
2OR X4.2 B A + B
3AND G2.2 C
(A + B)⋅C
4 WRT Y11 .1 W1 output
(A + B)⋅C
5 WRT Y14 .6 W2 output
(A + B)⋅C
CAUTION
In each WRT,WRT.NOT instruction, specify different
address. Double coil, which means a coil with an
address is often used in one ladder program, may
occur trobles of the execution timing in the sequence
program. Don't use "double coil".