
4.LADDER LANGUAGE B-63983EN/02
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Table 4.4.3 Mnemonic of CTRC instruction
Mnemonic format Memory status of control condition
Step
number
Instruction
Address
No.
Bit No. Remarks ST3 ST2 ST1 ST0
1RD ¡¡¡¡ .¡ CN0 CN0
2 RD. STK ¡¡¡¡ .¡ UPDOWN CN0 UPDOWN
3 RD. STK ¡¡¡¡ .¡ RST CN0 UPDOWN RST
4 RD. STK ¡¡¡¡ .¡ ACT CN0 UPDOWN RST ACT
5 SUB 55 CTRC instruction
6(PRM) ¡¡¡¡ Counter preset value
address
7(PRM) ¡¡¡¡ Counter register address
8WRT ¡¡¡¡ .¡ Count up output W1
Control conditions
(a) Specifying the initial value (CN0)
CN0 = 0: The count value starts with "0". 0, 1, 2, 3, . . . n
CN0 = 1: The count value starts with "1". 1, 2, 3, . . . n
(b) Specifying up or down count (UPDOWN)
UPDOWN = 0:
Up counter.
The initial value is "0" when CN0 = 0 or "1" when CN0 = 1.
UPDOWN = 1:
Down counter. The initial value is the preset value.
(c) Reset (RST)
RST = 0: Reset cancelled.
RST = 1: Reset. W1 is reset to "0". The accumulated value is
reset to the initial value.
(d) Count signal (ACT)
ACT = 0: The counter does not operate. W1 does not change.
ACT = 1: The counter operates at the rise of this signal.
Parameters
(a) Counter preset value address
The first address of the counter preset value field is set.
The continuous 2-byte memory space from the first address is
required for this field. Field D is normally used.
Counter
reset value+0
CTR: Preset value
(0 to 32,767)
Counter
reset value+1
CTR
The counter preset value is binary. Therefore, it ranges from 0 to
32,767.