
4.LADDER LANGUAGE B-63983EN/02
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(b) Reset (RST)
RST=0: Disables reset.
RST=1: Sets error output W1 to 0. That is, when a parity error
occurs, setting RST to 1 results in resetting.
(c) Execution command (ACT)
ACT=0: Parity checks are not performed. W1 does not alter.
ACT=1: Executes the PARI instruction, performing a parity
check.
Error output (W1)
If the results of executing the PARI instruction is abnormal, W1=1 and
an error is posted. The W1 address can be determined arbitrarily.
Example of using the PARI instruction
Fig. 4.8.7 (b) shows odd-parity checking of a code signal entered at
address X036.
0
7
6 5 4 3 2 1 0
ddress X036
6-bit code signal
Odd-parity bit
PARI
SUB 11
X036
R228.0
ERST.M
X32.7
TF
F7.3
ERR
R228.0
R228.0
R228.0
Fig. 4.8.7 (b) Ladder diagram for the PARI instruction
NOTE
For bits 0 to 7, bits other than those for the parity
check must be 0.