
1.OVERVIEW OF PMC B-63983EN/02
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Difference in signal status between 1st level and 2nd level sequence parts
The status of the same input signal may become different between the
1st and 2nd level sequence parts. The 1st level sequence part uses the
input signal memory for signal processing while the 2nd level sequence
part uses the 2nd level synchronous input signal memory. Therefore, it
is possible that an input signal for the 2nd level sequence part lags
behind the input signal for the 1st level sequence part by a cycle of the
2nd level sequence execution at the worst.
When creating a sequence program, note the following:
Signal status
A.M On (pulse signal with short pulse width in time)
B Off
C On
When the 1st level is executed, the following difference can occur
between Fig. 1.4.5 (d) and Fig. 1.4.5 (e):
(1) For Fig. 1.4.5 (d)
Even when W1 = 1, W2 may not be 1. (This is because the A.M
signal may differ between the 1st level and 2nd level.)
(2) For Fig. 1.4.5 (e)
If W1 = 1, W2 is always 1.
When performing the sequence shown in Fig. 1.4.5 (d), do the
following:
At the 1st level, perform the high-speed sequence processing
applied when the A.M signal status changes (operating).
At the 2nd level, perform the sequence processing applied when
the A.M signal status does not change (stopped).
NOTE
In the middle of 1st level processing, a signal status
change may occur asynchronously with the
sequence program processing. For details, see
Subsection 1.4.7.